/**
  ******************************************************************************
  * @file    24l01.h
  * @author  lilianfu <lilianfu@msn.com>
  * @version V1.0.0
  * @date    18-Ocoober-2016
  * @brief   NORDIC nRF24L01 Single Chip 2.4Ghz Transceiver Driver
  ******************************************************************************
  * @attention
  * Class declaration for nRF24L01 and helper enums
  * Datasheet:
  * http://www.nordicsemi.com/eng/nordic/content_download/2730/34105/file/nRF24L01_Product_Specification_v2_0.pdf
  ******************************************************************************
  */
#ifndef __24L01_H
#define __24L01_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32f10x.h"
#define NRF24L01_READ_REG        0x00  /*Read register ,LSB 5 bits*/
#define NRF24L01_WRITE_REG       0x20  /*Write register, LSB 5 bits*/
#define NRF24L01_RD_RX_PLOAD     0x61  /*Read valid data 1~32 bytes*/
#define NRF24L01_WR_TX_PLOAD     0xA0  /*Write valid data 1~32 bytes*/
#define NRF24L01_FLUSH_TX        0xE1  /*Clean TX FIFO register,use in Transmit mode*/
#define NRF24L01_FLUSH_RX        0xE2  /*Clean RX FIFO register,use in Receive mode*/
#define NRF24L01_REUSE_TX_PL     0xE3  /*Reuse previous package data,when CE pin is high,
										 package data transmit continuously.*/
#define NRF24L01_NOP             0xFF  /*NOP,use to read register*/
										 /* Register Map */
#define CONFIG          0x00  /* Configuration Register */
#define EN_AA           0x01  /* Enable ‘Auto Acknowledgment’ Function Disable 
								 this functionality to be compatible with nRF2401 */
#define EN_RXADDR       0x02  /* Enabled RX Addresses */
#define SETUP_AW        0x03  /* Setup of Address Widths (common for all data pipes) */
#define SETUP_RETR      0x04  /* Setup of Automatic Retransmission */
#define RF_CH           0x05  /* RF Channel */
#define RF_SETUP        0x06  /* RF Setup Register */
#define STATUS          0x07  /* Status Register (In parallel to the SPI command
								 word applied on the MOSI pin, the STATUS register
								 is shifted serially out on the MISO pin) */
#define OBSERVE_TX      0x08  /* Transmit observe register */
#define CD              0x09  /* Carrier Detect */
#define RX_ADDR_P0      0x0A  /* Receive address data pipe 0. 5 Bytes maximum
								 length. (LSByte is written first. Write the number
								 of bytes defined by SETUP_AW) */
#define RX_ADDR_P1      0x0B  /* Receive address data pipe 1. 5 Bytes maximum
								 length. (LSByte is written first. Write the number
								 of bytes defined by SETUP_AW) */
#define RX_ADDR_P2      0x0C  /* Receive address data pipe 2. Only LSB. MSBytes
								 is equal to RX_ADDR_P1[39:8] */
#define RX_ADDR_P3      0x0D  /* Receive address data pipe 3. Only LSB. MSBytes
								 is equal to RX_ADDR_P1[39:8] */
#define RX_ADDR_P4      0x0E  /* Receive address data pipe 4. Only LSB. MSBytes
								 is equal to RX_ADDR_P1[39:8] */
#define RX_ADDR_P5      0x0F  /* Receive address data pipe 5. Only LSB. MSBytes
								 is equal to RX_ADDR_P1[39:8] */
#define TX_ADDR         0x10  /* Transmit address. Used for a PTX device only.
								 (LSByte is written first)
								 Set RX_ADDR_P0 equal to this address to handle
								 automatic acknowledge if this is a PTX
								 device with Enhanced ShockBurst™ enabled. */
#define RX_PW_P0        0x11  /*  */
#define RX_PW_P1        0x12  /*  */
#define RX_PW_P2        0x13  /*  */
#define RX_PW_P3        0x14  /*  */
#define RX_PW_P4        0x15  /*  */
#define RX_PW_P5        0x16  /*  */
#define FIFO_STATUS     0x17  /* FIFO Status Register */
#define DYNPD           0x1C  /* Enable dynamic payload length */
#define FEATURE         0x1D  /* Feature Register */

								 /* Register Bit Mast */
								 /* CONFIG 0x00 */
#define MASK_RX_DR            6
#define MASK_TX_DS            5
#define MASK_MAX_RT           4
#define EN_CRC                3
#define CRCO                  2
#define PWR_UP                1
#define PRIM_RX               0
/* EN_AA 0x01 */
#define ENAA_P5               5
#define ENAA_P4               4
#define ENAA_P3               3
#define ENAA_P2               2
#define ENAA_P1               1
#define ENAA_P0               0
/* EN_RXADDR 0x02 */
#define ERX_P5                5
#define ERX_P4                4
#define ERX_P3                3
#define ERX_P2                2
#define ERX_P1                1
#define ERX_P0                0
/* SETUP_AW 0x03 */
#define AW                    0
#define SETUP_AW_3BYTES    0x01
#define SETUP_AW_4BYTES    0x02
#define SETUP_AW_5BYTES    0x03
/* SETUP_PETR 0x04 */
#define ARD                   4
#define ARC                   0
#define RETRANSMIT_250US   0x00
#define RETRANSMIT_500US   0x01
#define RETRANSMIT_750US   0x02
#define RETRANSMIT_1000US  0x03
#define RETRANSMIT_1250US  0x04
#define RETRANSMIT_1500US  0x05
#define RETRANSMIT_1750US  0x06
#define RETRANSMIT_2000US  0x07
#define RETRANSMIT_2250US  0x08
#define RETRANSMIT_2500US  0x09
#define RETRANSMIT_2750US  0x0A
#define RETRANSMIT_3000US  0x0B
#define RETRANSMIT_3250US  0x0C
#define RETRANSMIT_3500US  0x0D
#define RETRANSMIT_3750US  0x0E
#define RETRANSMIT_4000US  0x0F
/* RF_CH 0x05 */
#define RF_CHANNEL            0
/* RF_SETUP 0x06 */
#define PLL_LOCK              4
#define RF_DR                 3
#define RF_PWR                6
#define RX_DR                 6
#define TX_DS                 5
#define MAX_RT                4
#define RX_P_NO               1
#define TX_FULL               0
/* OBSERVE_TX 0x08 */
#define PLOS_CNT              4
#define ARC_CNT               0
/* CD 0x09 */
#define CARRIER_DETECT        0
/* FIFO_STATUS 0x17 */
#define TX_REUSE              6
#define FIFO_FULL             5
#define TX_EMPTY              4
#define RX_FULL               1
#define RX_EMPTY              0
/* DYNPD 0x1C */
#define DPL_P5	              5
#define DPL_P4	              4
#define DPL_P3	              3
#define DPL_P2	              2
#define DPL_P1	              1
#define DPL_P0	              0
/* FEATURE 0x1D */
#define EN_DPL	              2
#define EN_ACK_PAY            1
#define EN_DYN_ACK            0
/*  */
#define MAX_TX  		0x10  /*interrupt by max transmit times*/
#define TX_OK   		0x20  /*transmit conpile interrupt*/
#define RX_OK   		0x40  /*receive compile interrupt*/

/* define nRF24L01 pin */
#define NRF24L01_IRQ  (GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_5))
#define Set_NRF24L01_CE  {GPIO_SetBits(GPIOA,GPIO_Pin_4);}
#define Clr_NRF24L01_CE  {GPIO_ResetBits(GPIOA,GPIO_Pin_4);}
#define Set_NRF24L01_CSN  {GPIO_SetBits(GPIOC,GPIO_Pin_4);}
#define Clr_NRF24L01_CSN  {GPIO_ResetBits(GPIOC,GPIO_Pin_4);}
/*  */
#define TX_ADR_WIDTH    5   /*5 bytes address width*/
#define RX_ADR_WIDTH    5   /*5 bytes address width*/
#define TX_PLOAD_WIDTH  32  /*20 byte usr data width*/
#define RX_PLOAD_WIDTH  32  /*20 byte usr data width*/
/* Function */
	void NRF24L01_Init(void);                                             /*initial nRF24L01*/
	void RX_Mode(void);                                                   /*Receive mode*/
	void TX_Mode(void);                                                   /*Transmit mode*/
	uint8_t NRF24L01_Write_Buf(uint8_t reg, uint8_t *pBuf, uint8_t len);  /*Write buffer*/
	uint8_t NRF24L01_Read_Buf(uint8_t reg, uint8_t *pBuf, uint8_t len);   /*Read buffer*/
	uint8_t NRF24L01_Read_Reg(uint8_t reg);			                      //Read register
	uint8_t NRF24L01_Write_Reg(uint8_t reg, uint8_t value);               /*Write register*/
	uint8_t NRF24L01_Check(void);                                         /*check nRF24L01 connect to the MCU*/
	uint8_t NRF24L01_TxPacket(uint8_t *txbuf);                            /*Transmit a data package*/
	uint8_t NRF24L01_RxPacket(uint8_t *rxbuf);                            /*Received a data package*/
#ifdef __cplusplus
}
#endif
#endif /* __24L01_H */
